The present invention relates generally to the fabrication of semiconductor devices, and more particularly to methods and structures that implements air gaps in the dielectric layers.
As semiconductor devices continue to shrink the corresponding reduction in interconnect linewidths has increased line resistance. The reduced spacing between interconnects further creates more parasitic capacitance. This results in circuit signal delay and lower chip speed and performance.
In order to reduce the BEOL (back end of line) interconnect portion of circuit delay, the conventional silicon dioxide dielectric (k of approximately 4.0) is being replaced with dense lower-k films with k values of approximately 3.0. For further performance improvement, more dielectric capacitance is required (k less than 2.5) for advanced devices.
Capacitance improvements can be made with new porous low k dielectrics, however most of the porous materials have relatively weak mechanical properties as compared to dense dielectrics. It is also a significant challenge for the current BEOL process to integrate these materials with other module processes. For example, the conventional CMP (chemical mechanical polish) process has difficulty polishing a low mechanical-module porous dielectric, and the conventional PVD (plasma vapor deposition) diffusion barrier deposition technology cannot offer reasonable coverage on the surface of porous dielectrics.
Another technique to improve capacitance by lowering the dielectric constant is the creation of air gaps between conducting lines. While silicon dioxide has a dielectric constant of about and greater, the dielectric constant of air is approximately 1.
U.S. Pat. No. 5,949,143 (Bang) forms air gaps between two adjacent interconnects. The air gap is covered by a diffusion barrier layer and then by an insulating layer to allow the integration with upper interconnect levels.
U.S. Pat. No. 6,440,839 (Partovi) forms small air gaps between two adjacent interconnections by using “tenon-wetting” sidewall spacers on the interlevel dielectric to inhibit deposition of metal. This technique is limited to forming small air gaps between two widely-spaced interconnects.
U.S. Pat. No. 6,861,332 (Park) discloses the use of an exhaust vent to form an air gap in the dielectric.
U.S. Pat. No. 6,780,753 (Latchford) forms air gaps by depositing a dielectric material between the conductors, depositing a porous layer over the conductors and dielectric, and then stripping the dielectric material out of the space between the conductors through the porous layer leaving air gaps between the conductors.
U.S. Pub. No. 2005/0062165 (Saengar) forms closed air gap interconnect structures.
U.S. Pub. No. 2006/0019482 (Su) forms air gaps between a plurality of dummy stakes and a plurality of metal lines.
Therefore a need exists for a structure that enhances the reliability of the interconnection which is compatible with current BEOL processing.
An object of the present invention is to provide performance and capacitance improvements by creating air gaps inside dense dielectric materials.
Another object of the present invention is to provide these improvements without new or exotic porous dielectric materials and in a manner compatible with current BEOL processing.